Content addressable memory (CAM) arrays are known in the art and are utilized to store the addresses of defective rows or columns of a core memory array and/or circuit operational mode control bits. Multiple addresses of the arrays are accessed at a time to retrieve a full eight bit address.
CAM arrays are often found in FLASH memory arrays. Since the size of a CAM cell is not a significant overhead issue, a read current which is higher than that needed for a FLASH memory cell is desirable. CAM cells for FLASH memories typically are created from multiple FLASH cells. In common ground array architectures, the drains of each FLASH cell are independent. Thus, each CAM cell is formed of a column of multiple FLASH cells and neighboring columns form neighboring CAM cells. Since the drains are independent, the CAM cells can be accessed simultaneously.
Virtual ground architectures do not have independent drains. Instead, neighboring columns share bit lines and the bit lines can act as either a source or drain depending on the type of voltage provided to it. As a result, a CAM array cannot be easily produced with the virtual ground architecture although a CAM array can be produced for a virtual ground core memory array using a different cell design.
One example of a virtual ground architecture is the alternate metal, virtual ground architecture in which there are two bit lines for every metal line. To achieve this, there are some bit lines which are not metal clad and there are select transistors connecting the metal lines to these non-metal bit lines.